1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of removing a photoresist.
2. Description of the Related Art
Due to the increasingly high integration of ICs, chips simply cannot provide sufficient area for manufacturing interconnections. Therefore, in accord with the increased interconnects manufacturing requirements of miniaturized MOS transistors, it is increasingly necessary for IC manufacturing to adopt a design with more than two conductive layers. Generally, an inter-metal dielectric (IMD) layer is used to electrically isolate two adjacent conductive layers from each other. Moreover, a conductive layer used to electrically connect the two adjacent metal layers is called a via plug.
Typically, a sandwich structure of conductive material-insulating material-conductive material between two adjacent conductive layers in multilevel interconnects would lead to the parasitic capacitor effect. The parasitic capacitor effect induces resistor-capacitor time delay (RC time delay), so that the operation rate of the device is slow. In order to reduce the parasitic capacitor effect, it is necessary to form an IMD layer with a low dielectric constant between two adjacent conductive layers. Preferably, the material used to form dielectric layer with low dielectric constant is a flowable oxide.
Currently, the IMD layer includes many layers. Usually, the IMD layer is composed of a barrier oxide layer conformal to the interconnects, a flowable oxide layer over the barrier oxide layer and a cap oxide layer over the flowable oxide layer. Sometimes, it further comprises an insulating layer between the flowable oxide layer and the cap oxide layer. The structure of the IMD layer mentioned above provides an insulating material with a relatively low dielectric constant between two adjacent conductive layers. Hence, the parasitic capacitance between two adjacent conductive layers can be reduced.
Conventionally, the method of manufacturing a via plug comprises the steps of forming a via hole in the IMD layer exposed by a patterned photoresist to expose the subjacent interconnects. The photoresist is stripped away by oxygen (O.sub.2) plasma and the wafer is cleaned with solvent to remove residual photoresist. While the O.sub.2 plasma process is performed to strip away the photoresist, portions of the flowable oxide layer exposed by the via hole are bombarded by the O.sub.2 plasma. After the wafer is cleaned with solvent, the number of Si--H bonds in the flowable oxide layer is decreased and that of Si--OH bonds in the flowable oxide layer is increased.
The decrease of Si--H bonds in the flowable oxide layer leads to the increase of the dielectric constant of the flowable oxide layer. Therefore, the parasitic capacitance between two adjacent conductive layers and RC time delay are also increased. Moreover, the operation rate of the device becomes slow. Additionally, the increment of Si--OH bonds in the flowable oxide layer means that water absorption by the surface of the flowable oxide layer is increased. While the via hole is filled with the conductive material in subsequent processes, the water absorbing on the surface of the flowable oxide layer is transformed into bubbles in the via plug because the temperature is high. Because of the bubbles, the conductive material fails to fill the via hole, which is called a blind contact. The open circuit caused by a blind contact occurs between two adjacent conductive layers that should be electrically coupled to each other. Hence, errors occur when the devices are used and the devices cannot be controlled.